With development of the Internet, traffic of a telecommunications backbone network increases explosively at a speed of 50% to 80% each year, and there is an increasingly high requirement of bandwidth on an Ethernet interface in future.
Architectures proposed in current Ethernet standards are mainly architectures described in standards such as The Institute of Electrical and Electronics Engineers (IEEE) 802.3ba/bj/bm. Physical layers of all these architectures use an interface of 100 gigabit (G) bandwidth to perform forward error correction (FEC) encoding and decoding. In the prior art, an Ethernet interface architecture uses 100 G processing bandwidth, and main modules at a physical coding sublayer (PCS) have an encoding and decoding module, a scrambling module, a delivery module, an alignment marker insertion module, and the like. This solution is designed for 100 G bandwidth.
In an Ethernet architecture in the prior art, input data at the PCS layer that uses a 100 G transmission rate is parallel data in a 100 G Ethernet media independent interface (Century Gigabit Media Independent Interface (CGMII)) format at a reconciliation sublayer (RS). Data in multiple lanes is output, and then the data is delivered to a physical medium attachment sublayer (PMA). Main functions of a receive side and a transmit side at the PCS layer may be based on extension of a 100 G standard. A 100 G transmit end first performs 64b/66b encoding on data, and then scrambles and delivers the data. To resolve problems of alignment in lanes and disorder between lanes, the 100 G transmit end further needs to insert bit interleaved parity (BIP) codes as alignment markers (AM), and delivers the data to PMA lanes after inserting the AMs. A 100 G receive end first receives the data, performs block alignment and locking and AM locking and alignment, then performs remapping on lanes using the AMs, removes the AMs after completing remapping of the lanes, and finally completes 64b/66b decoding. That is, in the foregoing prior art, the 100 G receive end completes remapping of the lanes according to the AMs after performing AM alignment and locking; therefore, the AMs can be identified by the receive end only when it is ensured that AM patterns are complete.
An existing Ethernet architecture may transmit a complete AM when being applicable to 100 G processing bandwidth; however, a structure of the foregoing architecture is simple, only limited scenarios are supported, and the architecture cannot be flexibly adapted and cannot be extended to high bandwidth. If an Ethernet interface uses a higher rate (for example, 400 G), problems such as that transmission bandwidth of a serializer/deserializer (Serdes) is not matched and that AMs cannot be aligned are likely to occur. Particularly, after FEC is introduced to the Ethernet, original AMs may be disorganized; as a result, the receive end cannot correctly identify the AMs, and therefore cannot complete remapping of the lanes, and a problem that the receive end cannot correctly perform decoding occurs.